Layout Reconstruction of Complex Silicon Chips
- S. Blythe, B. Fraboni, S. Lall, H. Ahmed and U. de Riu.
- IEEE Journal of Solid State Circuits, V. 28, No. 2, p. 138--145, 1993.
A semiautomated, fast turnaround, and high reliability procedure for the layout reconstruction of complex VLSI circuits is presented together with details of the equipment and processes employed. The techniques have been verified using both simple CMOS gate array chips and complex VLSI microprocessor circuits and may be applied, in principle, to arbitrarily large or complex devices.